1. Field of the Invention
The present invention relates to structure structures and fabrication methods thereof, and more particularly, to a substrate structure having an insulating layer and a fabrication method thereof.
2. Description of Related Art
Along with the progress of semiconductor packaging technologies, various package types have been developed for semiconductor devices. Particularly, BGA (Ball Grid Array) technologies, such as PBGA, EBGA and FCBGA technologies, are advanced semiconductor packaging technologies and characterized in that a semiconductor device and a plurality of solder balls are mounted on opposite surfaces of a packaging substrate. The solder balls are arranged in a grid array on the packaging substrate so as to achieve more I/O connections per unit area and hence meet the high integration requirement of semiconductor chips. Further, the overall package can be electrically connected to an external electronic device through the solder balls.
In addition, as semiconductor packages are developed toward miniaturization, multi-function, high speed and high frequency, circuit boards (or packaging substrates) used in the semiconductor packages are developed toward fine pitch.
FIG. 1 is a schematic cross-sectional view of a conventional packaging substrate 1. Referring to FIG. 1, a substrate body 10 having a plurality of conductive pads 100 and circuits 101 is provided. A solder mask layer 11 is formed on the substrate body 10 and a plurality of openings 110 are formed in the solder mask layer 11 for correspondingly exposing the conductive pads 100. The openings 110 have a projective width R less than the width A of the corresponding conductive pads 100. Thereafter, a plurality of solder balls 13 are formed on and electrically connected to the conductive pads 100. As such, a packaging substrate 1 used for a flip-chip package is achieved. By reflowing the solder balls 13, the packaging substrate can be electrically connected to an electronic element, such as a semiconductor chip (not shown).
By using the solder balls 13 as interconnection elements, the conventional packaging substrate 1 has shortened electrical transmission paths, reduced package size and improved electrical performance.
However, during the reflow process, the solder material of the solder balls 13 easily expands outward along the circuits 101 and flows to the bottom of the solder mask layer 11. Since the solder mask layer 11 and the solder balls 13 are made of different materials, a CTE (Coefficient of Thermal Expansion) difference therebetween easily causes cracking of the solder mask layer 11, for example, a crack K of FIG. 1. As such, chemicals used in the process easily come into contact with the substrate body 10 through the crack K and consequently contaminate the substrate body 10. Further, moisture may enter into the substrate body 10 through the crack K and cause an oxidization of the circuits 101 or a short circuit.
Further, in a reliability test (such as high temperature storage or drop), stress variation easily occurs to the crack K of the solder mask layer 11 and causes problems such as large-area cracking and poor quality of the solder mask layer 11.
In addition, referring to FIG. 1′, the projective width R′ of the openings 110′ can be greater than the width A of the conductive pads 100 so as to completely expose the conductive pads 100, thereby preventing the solder material of the solder balls 13 from flowing along the circuits 101 to the bottom of the solder mask layer 11. However, if the projective width R′ of the openings 110′ is not large enough, the solder balls 13 may still compress the solder mask layer 11 and result in large-area cracking and poor quality of the solder mask layer 11. On the other hand, although the projective width R′ of the openings 110′ can be further increased to overcome the above-described problems, it will reduce the space on the substrate body 10 for wiring and easily cause delamination of the conductive pads 100.
Similarly, the above-described problems may occur between the solder balls 13 and the semiconductor chip.
Therefore, there is a need to provide a substrate structure and a fabrication method thereof so as to overcome the above-described drawbacks.